EDN

Verific Design Automation’s Netlist Only Parser, Database

Verific Design Automation, best known for its Verilog, SystemVerilog and VHDL parsers and elaborators, today said that its Netlist Only Parser is gaining momentum among electronic design automation ...
Design-Reuse

Domain Technologies announces Synthesizable MRAM8051 Microcontroller Netlist Library for Actel FPGAs Including Royalty-Free License for use in Tekmos Merged ASICs

Plano, Texas , October 12, 2006 - Domain Technologies announces the availability of the industry's first, royalty-free, synthesizable MCS8051 code-compatible microcontroller netlist library and ...
EDN

Ten-million-gate switched fabric needs better verification

Because Onex is a startup, our design and verification teams require efficient design flows and methodology to be effective. During the design phase of the company's service processor, the Switch ...
Design-Reuse

Pitfalls for Logical Equivalence Check

The VLSI design cycle is partitioned into two phases i.e. front-end and back-end phases of the complete SoC design cycle. While at front-end, most of the architectural specifications, coding and ...